1. Field of the Invention
The present invention generally relates to integrated semiconductor memory devices, and more particularly to a dynamic random-access memory including a circuit arrangement for generating a potential-raised or boosted voltage employed to drive word lines thereof.
2. Description of the Related Art
With the increasing needs for high performance and reliability of digital computer systems, development of a semiconductor memory with a large capacity has been demanded strongly. The design of dynamic random-access memories (DRAMs) has been developed along with such a trend. A presently available DRAM includes an array of memory cells that are arranged in rows and columns. Each memory cell has a capacitor and an insulated-gate transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET). The capacitor acts as a data storage element; the transistor serves as a data transfer gate
Parallel data transfer lines are provided and connected to the current carrying electrodes of cell transistors in columns of memory cells. Parallel control lines are associated with the control electrodes of rows of memory cells. When a control line is activated, and a certain data transfer line is selected, the transistor in a selected memory cell is rendered conductive to "transfer" digital information from a corresponding data transfer line to the cell capacitor therein. The information is thus stored in the selected memory cell. The data transfer lines are called "bit lines"; the control lines are called "word lines."
A high ("H") voltage that is supplied via the word lines to the control gates of memory cell transistors should be arranged to be potentially greater in magnitude than the information voltage of high level on the bit lines. The difference between the voltages is necessary in order to compensate for a potential drop of a word-line drive voltage due to the threshold voltages of the memory cell transistors. The high voltage is generated using a specific capacitor that is arranged within a word-line drive circuit. The capacitor may act as the "booting" or bootstrap capacitor for producing a word-line drive voltage that is higher than the power supply voltage Vcc of DRAM.
Generally, the bootstrap capacitor is precharged at its one electrode toward the power supply voltage; the other electrode thereof is initially at the ground potential, and then driven to rise up to the power supply voltage, thereby producing the word-line drive voltage of a suitable potential level. With such a voltage booting system, a difference arises between the dependency of the bit-line "H" level voltage on the power supply voltage, and that of the word-line "H" level voltage on the same. More specifically, the changing rate of the word-line "H" level voltage to the power supply voltage being varied is normally greater than that of the bit-line "H" level voltage. Assuming that the power supply voltage Vcc varies within the allowable range defined between the minimum voltage Vccmin and the maximum voltage Vccmax, "H" level voltage on word lines increases more rapidly than the "bit-line H" level voltage does. As a result, the potential difference between these "H" voltages can no longer hold a constant value.
If the potential difference were arranged to have a desired value at the minimum power supply voltage Vccmin, when the power supply voltage is at the maximum level Vccmax, the word-line "H" level voltage goes beyond its limit value. This applies unnecessary potential stress to the gate insulation layers of the cell transistors; in the worst case, these cell transistors will be dielectrically broken down. Such undesirable phenomenon has been known as the "time dependent dielectric breakdown (TDDB)" among those skilled in the art.
On the contrary, to eliminate the TDDB phenomenon, it may be considered that the above potential difference were set at a suitable value at the maximum level Vccmax. If this is the case, however, another problem arises. When the power supply voltage Vcc drops to the maximum level Vccmax, the word-line "H" voltage can no longer maintain a suitable potential level that is higher than the bit-line "H" voltage as required. This makes it insufficient, or impossible, for the word-line drive voltage to compensate for a potential decrease in the threshold values of the memory cell transistors. As 5 a result, the "H" data-writing performance decreases in the DRAMs.
In the conventional DRAMs, the above-mentioned "TDDB" problems have not been so serious for the semiconductor manufacturers. This can be said because the memory integration density itself has been kept lower. Low density of memory cells may permit each cell to be designed rather roughly to be greater in the chip area and in the gate-insulation film thickness. The dielectric breakdown level of the cell transistors thus has been high enough to "absorb" the excess potential increase in the word-line drive voltage, when the power supply voltage Vcc varies at the maximum level Vccmax. However, this cannot be applied to he today's highly integrated DRAMs any more. As the number of bits increases in DRAMs, the cell size decreases, the gate insulation film thickness also decreases, and the magnitude of dielectric breakdown of the "transfer gate" transistor in each cell of necessity decreases. Therefore, it will become more difficult to eliminate the TDDB problem in the cell transistors and yet to provide high operating reliability in the entire region of the allowable variation range of the power supply voltage Vcc. The technical problem is a significant bar to development in highly integrated DRAMs.